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- Using MyHDL is a solution. A MyHDL design can be automatically converted to equivalent code in both Verilog and VHDL. Actually, using MyHDL and conversion is probably the best solution available for language-neutral design. It is obviously superior to manual conversion. Moreover, direct convertors between Verilog and VHDL don't work very well.
www.myhdl.org/start/why.html
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Is MyHDL a Python language?
- Short Description
- Modeling
- Simulation and Verification
- Conversion to Verilog and VHDL
MyHDL is a free, open-source package for using Python as a hardware descriptionand verification language. Python is a very high level language, and hardwaredesigners can use its full power to model and simulate their designs.Moreover, MyHDL can convert a design to Verilog or VHDL. This provides a pathinto a traditional design flow.
Python's power and clarity make MyHDL an ideal solution for high levelmodeling. Python is famous for enabling elegant solutions to complex modelingproblems. Moreover, Python is outstanding for rapid application developmentand experimentation. The key idea behind MyHDL modeling is the use of Python generators to modelhardware concurrency. Generators...
The built-in simulator runs on top of the Python interpreter. It supportswaveform viewing by tracing signal changes in a VCD file. With MyHDL, the Python unit test framework can be used on hardware designs.Although unit testing is a popular modern software verification technique, itis still uncommon in the hardware design world. MyHDL can also be u...
Subject to some limitations, MyHDL designs can be converted to Verilog or VHDL.This provides a path into a traditional design flow, including synthesis andimplementation. However, the convertible subset is much wider than thestandard synthesis subset, and includes features that can be used for highlevel modeling and test benches. The converter work...
May 15, 2015 · MyHDL is an open source platform developed by Jan Decaluwe for using Python, a general-purpose high-level language for hardware design. A designer using this software can benefit from the power of Python language as well as the merits of a free, open source software.
Oct 25, 2021 · MyHDL is already quite good at co-simulation through VPI, if you’re fine with the ‘upstream’ iverilog simulator support. When choosing VHDL, you might run into issues with arithmetics during translation (#322).
MyHDL supports sophisticated and high level modeling techniques. This is described in Chapter High level modeling . MyHDL enables the use of modern software verification techniques, such as unit testing, on hardware designs.
Nov 12, 2022 · my conclusion on pure python simulation and cosim is essentially that you have to do both all the time while developing. My first attempt was to develop all code in myhdl (pure python) and then feed the verilog translated from python into the toolchain onto a tinyfpga. → the result is disappointing and no clue why….
Apr 16, 2022 · MyHDL tries to lower the barrier to entry and improve on certain language features that make the task more difficult than necessary. The most important MyHDL design choice is to implement it as a Python library instead of as a separate language.
